This invention relates to operating a digital signal processor to limit samples of an electrical signal, each sample being represented by a complex signal. Such limiting is particularly useful for reducing co-channel interference (CCI) in communications systems.
CCI is constituted by one or more interfering signals within the frequency band of a desired signal in a communications system, and is a key factor that limits the frequency reuse capacity of mobile communications systems. The CCI can not be reduced by conventional filtering techniques, because it falls within the bandwidth of the desired signal. One technique, described in the copending application referred to above, for reducing CCI is limiting of a received complex signal which comprises a mixture of a desired FM (frequency modulated) signal and an independent weaker (i.e. lower average power) CCI. The desired signal has a constant envelope, whereas the received signal has a non-constant envelope due to the CCI. The complex signal limiter converts the input mixture to a constant envelope signal, transforming at least half of the CCI energy outside the bandwidth of the desired signal so that it can be filtered out by a low pass filter.
As described in the published international application referred to above, complex signal limiting is carried out in a dsp (digital signal processor) on each sample x(k) of the received complex signal, typically at a sampling rate of about 48 kHz, and consists of a calculation of the function ##EQU1## where x*(k) is the complex conjugate of x(k) and x.sub.lim (k) is the output of the complex signal limiter. As can be appreciated, the calculation of this non-linear function for each sample requires significant dsp resources.
An object of this invention is to provide an improved method of operating a digital signal processor to limit samples of an electrical signal in accordance with this function, using reduced dsp resources, and to provide an improved limiter.